Page tables can be limited to one page, more easily be paged out and multiple page faults possible. A simple technique is a two-level page table.

A logical address (on 32-bit machine with 4K page size) is divided into :

• a page number consisting of 20 bits
  
• a page offset consisting of 12 bits
  

Since the page table is paged, the page number is further divided into :

• a 10-bit page number
• a 10-bit page offset

Break up the virtual address space into multiple page tables Increase the utilization and reduce the physical size of a page table Not all address ranges will be used, some page tables need not be present. One may notice that multilevel page tables are still not a satifying solution, since every translation step must be made no matter how sparsely a table is filled It saves memory but costs time.